| 000 | 00959nam a2200277 i 4500 | ||
|---|---|---|---|
| 008 | 120320s2011 xx a 001 0 eng d | ||
| 020 | _a9780983497301 | ||
| 020 | _a0983497303 | ||
| 035 | _a(OCoLC)780536255 | ||
| 040 |
_aMEAUC _cMEAUC _dOCLCO _dYDXCP _dOCLCF _dBGZ _dBAUN _beng _erda |
||
| 049 | _aBAUN_MERKEZ | ||
| 050 | 0 | 0 |
_aTK7885.7 _b.R43 2011 |
| 100 | 1 | _aReadler, Blaine C. | |
| 245 | 1 | 0 |
_aVerilog by example : _ba concise introduction for FPGA design / _cBlaine C. Readler. |
| 246 | 3 | 0 | _aIntroduction for FPGA design. |
| 250 | _a1st editon | ||
| 264 | 1 |
_a[place of publication not identified]: _bFull Arc Press, _c2011. |
|
| 300 |
_a114 pages : _billustrations ; _c24 cm. |
||
| 336 |
_atext _btxt _2rdacontent |
||
| 337 |
_aunmediated _bn _2rdamedia |
||
| 338 |
_avolume _bnc _2rdacarrier |
||
| 500 | _aIncludes index. | ||
| 650 | 0 | _aVerilog (Computer hardware description language) | |
| 650 | 0 | _aField programmable gate arrays. | |
| 942 |
_2lcc _cKT |
||
| 999 |
_c33646 _d33646 |
||